OCVM=Val_0x0, ES1=Val_0x0, ES0=Val_0x0, SYSPLL=Val_0x0, CLK20M=Val_0x0, CLK100M=Val_0x0, CVM=Val_0x0, CLK38P4M=Val_0x0, HFXO=Val_0x0, CLK160M=Val_0x0
Clock Enable Register
| SYSPLL | Enable SYSPLL_CLK 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| ES0 | Enable RTSS_HP_CLK 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| ES1 | Enable RTSS_HE_CLK 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| HFXO | Enable clock to the HFXO_OUT pin 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| CLK160M | Enable 160M_CLK 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| CLK100M | Enable 100M_CLK 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| CLK20M | Enable USB_CLK and 10M_CLK 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| CLK38P4M | Enable HFOSC_CLK 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| CVM | Enable SRAM0 clock 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| OCVM | Enable SRAM1 clock 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |